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1/40 may 1999 M28W160t M28W160b 16 mbit (1mb x16, boot block) low voltage flash memory n supply voltage Cv dd = 2.7v to 3.6v: for program, erase and read Cv ddq = 1.65v or 2.7v: input/output option Cv pp = 12v: optional supply voltage for fast program and erase n access time C 3.0v to 3.6v: 100ns C 2.7v to 3.6v: 120ns n programming time: 10s typical n program/erase controller (p/e.c.) C program word-by-word C status register bits n common flash interface C 64 bit security code n otp memory area n memory blocks C parameter blocks (top or bottom location) C main blocks n block erase n block protection on two parameter blocks (selected without 12v supply) n program/erase suspend C read or program another block during program/erase suspend n program/erase latency time: <1s C data update on a word-by-word basis C efficient data read/write during program/erase suspend n fast recovery from power down n low power consumption C automatic stand-by: 10a max C stand-by: 10a max C 100,000 program/erase cycles per block n 20 years of data retention C defectivity below 1ppm/year n electronic signature C manufacturer code: 0020h C device code, M28W160t: 0090h C device code, M28W160b: 0091h tsop48 (n) 12 x 20mm bga48 (gj) 8 x 6 solder balls m bga figure 1. logic diagram ai02339b 20 a0-a19 w dq0-dq15 v dd M28W160t M28W160b e v ss 16 g rp wp v pp v ddq
M28W160t, M28W160b 2/40 figure 2a. bga connections (top view) note: although no solder ball is present where the unnamed dotted connections are placed (c4 and c5 locations), these are reserv ed for future use. routing should be avoided in this area. ai02338b g dq1 dq10 v dd dq4 dq13 dq7 v ss f v ss dq0 dq9 dq3 dq12 dq6 dq15 v ddq e a0 e dq8 dq2 dq11 dq5 dq14 a16 d a1 a3 a6 a9 a12 a15 c a2 a5 a17 a18 rp w a10 a14 b a4 a7 a19 wp v pp a8 a11 a13 a 8 7 6 5 4 3 2 1 figure 2b. tsop connections dq3 dq9 dq2 a6 dq0 w a3 a19 dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v dd dq4 dq5 a7 dq7 v pp wp ai02340c M28W160t M28W160b 12 1 13 24 25 36 37 48 dq8 nc nc a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ddq a15 a14 v ss e a0 rp v ss table 1. signal names a0-a19 address inputs dq0-dq7 data input/output, command inputs dq8-dq15 data input/output e chip enable g output enable w write enable rp reset / deep power-down wp write protect v dd supply voltage v ddq optional power supply for input/output buffers v pp optional supply voltage for fast program & erase v ss ground nc not connected internally
3/40 M28W160t, M28W160b description the M28W160 is a 16 mbit non-volatile flash memory that can be erased electrically at the block level and programmed in-system on a word-by- word basis. the device is offered in the tsop48 (12 x 20 mm) and the bga48 0.75 mm ball pitch packages. when shipped, all bits of the M28W160 are in the '1' state. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. each block can be programmed and erased over 100,000 cycles. v ddq allows to drive the i/o pin down to 1.65v. an optional 12v v pp power supply is provided to speed up the program phase at customer production line environment. an internal command interface (c.i.) decodes the instructions to access/modify the memory content. the program/erase controller (p/e.c.) automati- cally executes the algorithms taking care of the timings necessary for program and erase opera- tions. verification is performed too, unburdening the microcontroller, while the status register tracks the status of the operation. the following instructions are executed by the M28W160: read array, read electronic signa- ture, read status register, clear status register, program, block erase, program/erase suspend, program/erase resume, cfi query, read/pro- gram otp area. organisation the M28W160 is organised as 1 mbit by 16 bits. a0-a19 are the address lines; dq0-dq15 are the data input/output. memory control is provided by chip enable e , output enable g and write enable w inputs. a reset/power-down controls the hardware reset and the power-down. the upper two (or lower two) parameter blocks can be protected to secure the code content of the memory. wp controls protection and unprotection operations. memory blocks the device features an asymmetrical blocked ar- chitecture. the M28W160 has an array of 39 blocks: 8 parameter blocks of 4 kword and 31 main blocks of 32 kword. M28W160t has the pa- rameter blocks at the top of the memory address space while the M28W160b locates the parame- ter blocks starting from the bottom. the memory maps are shown in tables 3 and 4. the two upper parameter blocks can be protected from accidental programming or erasure, using wp . each block can be erased separately. erase can be suspended in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. depends on range. symbol parameter value unit t a ambient operating temperature (2) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 155 c v io input or output voltage C0.6 to v ddq +0.6 v v dd , v ddq supply voltage C0.6 to 4.2 v v pp program voltage C0.6 to 13.5 v
M28W160t, M28W160b 4/40 table 3. top boot block address size (kword) address range 4 ff000-fffff 4 fe000-fefff 4 fd000-fdfff 4 fc000-fcfff 4 fb000-fbfff 4 fa000-fafff 4 f9000-f9fff 4 f8000-f8fff 32 f0000-f7fff 32 e8000-effff 32 e0000-e7fff 32 d8000-dffff 32 d0000-d7fff 32 c8000-cffff 32 c0000-c7fff 32 b8000-bffff 32 b0000-b7fff 32 a8000-affff 32 a0000-a7fff 32 98000-9ffff 32 90000-97fff 32 88000-8ffff 32 80000-87fff 32 78000-7ffff 32 70000-77fff 32 68000-6ffff 32 60000-67fff 32 58000-5ffff 32 50000-57fff 32 48000-4ffff 32 40000-47fff 32 38000-3ffff 32 30000-37fff 32 28000-2ffff 32 20000-27fff 32 18000-1ffff 32 10000-17fff 32 08000-0ffff 32 00000-07fff table 4. bottom boot block address size (kword) address range 32 f8000-fffff 32 f0000-f7fff 32 e8000-effff 32 e0000-e7fff 32 d8000-dffff 32 d0000-d7fff 32 c8000-cffff 32 c0000-c7fff 32 b8000-bffff 32 b0000-b7fff 32 a8000-affff 32 a0000-a7fff 32 98000-9ffff 32 90000-97fff 32 88000-8ffff 32 80000-87fff 32 78000-7ffff 32 70000-77fff 32 68000-6ffff 32 60000-67fff 32 58000-5ffff 32 50000-57fff 32 48000-4ffff 32 40000-47fff 32 38000-3ffff 32 30000-37fff 32 28000-2ffff 32 20000-27fff 32 18000-1ffff 32 10000-17fff 32 08000-0ffff 4 07000-07fff 4 06000-06fff 4 05000-05fff 4 04000-04fff 4 03000-03fff 4 02000-02fff 4 01000-01fff 4 00000-00fff
5/40 M28W160t, M28W160b signal descriptions see figure 1 and table 1. address inputs (a0-a19). the address signals are inputs driven with cmos voltage levels. they are latched during a write operation. data input/output (dq0-dq15). the data in- puts, a word to be programmed or a command to the c.i., are latched on the chip enable e or write enable w rising edge, whichever occurs first. the data output from the memory array, the electronic signature or status register is valid when chip enable e and output enable g are active. the output is high impedance when the chip is dese- lected, the outputs are disabled or rp is tied to v il . commands are issued on dq0-dq7. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e at v ih deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at v il . output enable (g ). the output enable controls the data input/output buffers. write enable (w ). this input controls writing to the command register, input address and data latches. write protect (wp ). write protect is an input to protect or unprotect the two lockable parameter blocks. when wp is at v il , the lockable blocks are protected. program or erase operations are not achievable. when wp is at v ih , the lockable blocks are unprotected and they can be pro- grammed or erased (refer to table 9). reset/power down input (rp ). the rp input provides hardware reset of the memory and power down functions. when rp is at v il , the memory is in reset/deep power down mode. the outputs are put to high-z and the current consumption is min- imised. when rp is at v ih , the device is in normal operation. exiting reset/deep power down mode the device enters read array mode. v dd supply voltage (2.7v to 3.6v). v dd pro- vides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). it ranges from 2.7v to 3.6v. v ddq supply voltage (1.65v to v dd +0.3v). v ddq provides the power supply to the i/o pins and enables all outputs to be powered indepen- dently from v dd . v ddq can be tied to v dd or it can use a separate supply. it can be powered either from 1.65v to 2.2v or from 2.7v to 3.6v. v pp program supply voltage (12v). v pp is the power supply for program and erase operations. the M28W160 is intended to execute program and erase operations at v dd voltage ranges. nev- ertheless, customers wishing to speed up pro- gramming at their manufacturing environment can also apply 12v to v pp . this is not intended for ex- tended use. v pp can be connected to 12v for a total of 80 hours maximum. 12v may be applied to v pp dur- ing program and erase for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. stressing the device beyond these limits could damage the device. v pp may be tied to 5v during read or idle phases. 5v supply is forbidden for program or erase oper- ations. the v pp must be supplied with either 2.7v to 3.6v or 11.4v to 12.6v during programming or erase operations. v pp can be tied to v ss to achieve a complete block protection. v ss ground. v ss is the reference for all the volt- age measurements.
M28W160t, M28W160b 6/40 device operations four control pins rule the hardware access to the flash memory: e , g , w , rp . the following operations can be performed using the appropriate bus cycles: read, write the com- mand of an instruction, output disable, standby, power down (see table 5). read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register and the cfi. both chip enable (e ) and output enable (g ) must be at v il in order to perform the read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output independently of the device selection. the data read depend on the previous command written to the memory (see instructions rd, rsig, rsr, rcfi and rdo). read array is the default state of the device when exiting power down or af- ter power-up. write. write operations are used to give com- mands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e and write enable w are at v il with output enable g at v ih . commands, input data and addresses are latched on the rising edge of w or e , whichever occur first. output disable. the data outputs are high im- pedance when the output enable g is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in standby when chip enable e is at v ih and the device is in read mode. the power consumption is reduced to the standby level and the outputs are set to high im- pedance, independently from the output enable g or write enable w inputs. if e switches to v ih dur- ing program or erase operation, the device enters in standby when finished. power down. during power down all internal cir- cuits are switched off, the memory is deselected and the outputs are put in high impedance. the memory is in power down when rp is at v il . the power consumption is reduced to the power down level, independently from the chip enable e , out- put enable g or write enable w inputs. if rp is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid as it has been compromised by the aborted operation. table 5. user bus operations (1) note: 1. x = v il or v ih , v pph = 12v 5% . table 6. read electronic signature (rsig instruction) note: 1. rp = v ih . operation e g w rp wp v pp dq15-dq0 read v il v il v ih v ih x don't care data output write v il v ih v il v ih x v dd or v pph data input output disable v il v ih v ih v ih x don't care hi-z standby v ih xx v ih x don't care hi-z power down x x x v il x don't care hi-z code device e g w a0 a19-a1 dq15-dq8 dq7-dq0 manufact. code v il v il v ih v il don't care 00h 20h device code M28W160t v il v il v ih v ih don't care 00h 90h M28W160b v il v il v ih v ih don't care 00h 91h
7/40 M28W160t, M28W160b instructions and commands twelve instructions are available (see tables 7 and 8) to perform read memory array, read sta- tus register, read electronic signature, cfi que- ry, erase, program, clear status register, program/erase suspend, program/erase re- sume, read otp, program otp. status register output may be read at any time, during program- ming or erase, to monitor the progress of the oper- ation. an internal command interface (c.i.) decodes the instructions while an internal program/erase con- troller (p/e.c.) handles all timing and verifies the correct execution of the program and erase in- structions. p/e.c. provides a status register whose bits indicate operation and exit status of the internal algorithms. the command interface is reset to read array when power is first applied, when exiting from power down or whenever v dd is lower than v lko . command sequence must be followed exactly. any invalid combination of commands will reset the device to read array. read (rd) the read instruction consists of one write cycle (refer to device operations section) giving the command ffh. next read operations will read the addressed location and output the data. when a device reset occurs, the memory is in read array as default. read status register (rsr) the status register indicates when a program or erase operation is complete and the success or failure of operation itself. issue a read status register instruction (70h) to read the status reg- ister content. the read status register instruction may be is- sued at any time, also when a program/erase op- eration is ongoing. the following read operations output the content of the status register. it is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. ad- ditionally, any read attempt during program or erase operation will automatically output the con- tent of the status register. read electronic signature (rsig) two codes identifying the manufacturer and the device can be read from the memory allowing pro- gramming equipment or applications to automati- cally match their interface to the characteristics of the M28W160. manufacturer and device code (electronic signature) can be read by a read electronic signature instruction. it uses 3 operations: a write operation issues the command 90h; it is followed by two read opera- tions to output the manufacturer and device codes. the manufacturer code, 20h, is output when the address line a0 is at v il . the device code is 0090h (top version) or 0091h (bottom version) and is output when a0 is at v ih (refer to table 4). other address inputs are ignored. the codes are output on dq0-dq15. return to read mode is achieved writing the read array command. cfi query (rcfi) the common flash interface query mode is en- tered by writing 98h. next read operations will read the cfi data. write a read instruction to return to read mode (refer to the common flash interface section). read otp area (rdo) the read otp area (rdo) instruction is a single write cycle instruction: as the command 80h is written the device will be driven in read otp mode. any successive read bus cycle will output the addressed otp word. to return in the read memory array mode write the read command ffh. table 7. commands hex code command 00h, 01h, 60h, 2fh, c0h invalid/reserved 10h alternative program set-up 20h erase set-up 30h otp program set-up 40h program set-up 50h clear status register 70h read status register 80h otp read 90h read electronic signature 98h cfi query b0h program/erase suspend d0h program/erase resume, or erase confirm ffh read array
M28W160t, M28W160b 8/40 erasing should not be attempted when v pp is not within the allowed range of values (v dd or v pph ) as the results will be uncertain. status register bit b3 returns a '1' if v pp is not within the allowed range of values when erasing is attempted and/or during erasing execution. refer to the signals de- scription section for details of the allowable rang- es. erase aborts if v pp drops out of the allowed range or rp turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. a clear status reg- ister instruction must be issued to reset b3 of the status register. during the execution of the erase by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) in- structions. table 8. instructions note: 1. x = don't care. 2. the first cycle of the rd, rsr, rsig or rcfi instruction is followed by read operations to read memory array, status register or electronic signature codes. any number of read cycle can occur after one command cycle. 3. signature address bit a0=v il will output manufacturer code. address bit a0=v ih will output device code. other address bits are ignored. mne- monic instruction cycles 1st cycle 2nd cycle operation address (1) data operation address data rd read memory array 1+ write x ffh read (2) read address data rsr read status register 1+ write x 70h read (2) x status register rsig read electronic signature 1++ write x 90h read (2) signature address (3) signature rcfi cfi query 1+ write x 98h read (2) cfi address query rdo read otp area 1+ write x 80h read (2) otp address otp data ee erase 2 write x 20h write block address d0h pg program 2 write x 40h or 10h write address data input pdo program otp area 2 write x 30h write otp address otp data input clrs clear status register 1 write x 50h pes program/erase suspend 1 write x b0h per program/erase resume 1 write x d0h erase (ee) block erasure sets all the bits within the selected block to '1'. one block at a time can be erased. it is not necessary to program the block with 00h as the p/e.c. will do it automatically before erasing. this instruction uses two write cycles. the first command written is the erase set up command 20h. the second command is the erase confirm command d0h. an address within the block to be erased is given and latched into the memory dur- ing the input of the second command. if the sec- ond command given is not an erase confirm, the status register bits b4 and b5 are set and the in- struction aborts. read operations output the status register after erasure has started. status register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. after completion the status register bit b5 returns '1' if there has been an erase failure.
9/40 M28W160t, M28W160b table 9. memory blocks protection truth table note: 1. notes:1.x' = don't care 2. rp is the reset/power down. 3. v pp is the program or erase supply voltage. 4. v ih /v il are logic high and low levels. 5. v pp must be also greater than the program voltage lock-out v pplk . table 10. status register bits note: logic level '1' is high, '0' is low. v pp (1,3) rp (2,4) wp (1,4) lockable blocks other blocks x v il x protected protected v il v ih x protected protected v dd or v pph (5) v ih v il protected unprotected v dd or v pph (5) v ih v ih unprotected unprotected mnemonic bit name logic level definition note p/ecs 7 p/e.c. status '1' ready indicates the p/e.c. status, check during program or erase, and on completion before checking bits b4 or b5 for program or erase success '0' busy ess 6 erase suspend status '1' suspended on an erase suspend instruction p/ecs and ess bits are set to '1'. ess bit remains '1' until an erase resume instruction is given. '0' in progress or completed es 5 erase status '1' erase error es bit is set to '1' if p/e.c. has applied the maximum number of erase pulses to the block without achieving an erase verify. '0' erase success ps 4 program status '1' program error ps bit set to '1' if the p/e.c. has failed to program a word. '0' program success vpps 3 v pp status '1' v pp invalid, abort vpps bit is set if the v pp voltage is not v pph nor v dd when a program or erase instruction is executed. '0' v pp ok pss 2 program suspend status '1' suspended on a program suspend instruction p/ecs and pss bits are set to '1'. pss remains '1' until a program resume instruction is given '0' in progress or completed bps 1 block protection status '1' program/erase on protected block, abort bps bit is set to '1' if a program or erase operation has been attempted on a protected block '0' no operation to protected blocks 0 reserved
M28W160t, M28W160b 10/40 program (pg) the memory array can be programmed word-by- word. this instruction uses two write cycles. the first command written is the program set-up com- mand 40h (or 10h). a second write operation latch- es the address and the data to be written and starts the p/e.c. read operations output the status register con- tent after the programming has started. the status register bit b7 returns '0' while the programming is in progress and '1' when it has completed. after completion the status register bit b4 returns '1' if there has been a program failure. programming should not be attempted when v pp is not within the allowed range of values (v dd or v pph ) as the re- sults will be uncertain. status register bit b3 re- turns a '1' if v pp is not within the allowed range of values when programming is attempted and/or during programming execution. refer to the sig- nals description section for details. programming aborts if v pp drops out of the al- lowed range or rp goes to v il . as data integrity cannot be guaranteed when the program opera- tion is aborted, the memory location must be erased and re-programmed. a clear status regis- ter instruction must be issued to reset b3 of the status register. during the execution of the program by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) in- structions. program otp area (pdo) the program otp area (pdo) instruction is a two write cycle instruction: the first code issues is the otp program setup command 30h, while during the second write cycle the otp selected address and the otp data to be written are applied to the device. the conventional read status register operation can be performed to monitor the end of the programming operation. to return in the read memory array mode write the read command ffh. clear status register (clrs) the clear status register uses a single write op- eration which clears bits b3, b4 and b5 to '0'. its use is necessary before any new operation when an error has been detected. note, also, that the read array command must be issued before data can be read from the memory array. the clear status register is executed writ- ing the command 50h. program/erase suspend (pes) as erase takes in the order of seconds to com- plete, a program/erase suspend instruction is provided. program/erase suspend interrupts the program/erase routine allowing read from and program to data belonging to a different block. program/erase suspend is accepted only during the program/block erase instruction execution. when a program/erase suspend command is written to the c.i., the p/e.c. freezes the program/ erase operation. program/erase resume (per) continues the program/erase operation. program/erase suspend consists of writing the command b0h without any specific address. the status register bit b2 is set to '1' when the program has been suspended. b2 is set to '0' in case the program is completed or in progress. the status register bit b6 is set to '1' when the erase has been suspended. b6 is set to '0' in case the erase is completed or in progress. the valid commands while erase is suspended are program/erase resume, program, read array, read status register, read identifier, cfi query. while program is suspended the same command set is valid except for program instruction. during program/erase suspend mode, the chip can be placed in a pseudo-standby mode by taking e to v ih . this reduces active current consumption. v pp must be maintained within the allowed range of values (v dd or v pph ) while program/erase is suspended. program/erase is aborted if v pp drops out of the allowed range or rp turns to v il and status register b5 and b3 are set. program/erase resume (per) if a program/erase suspend instruction was previ- ously executed, the program/erase operation may be resumed by issuing the command d0h. the status register bit b2/b6 is cleared when pro- gram/erase resumes. read operations output the status register after the program/erase is re- sumed. the suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from figures 9, 10, 11 and 12.
11/40 M28W160t, M28W160b table 11. program, erase times and program/erase endurance cycles (t a = 0 to 70c or C40 to 85c; v dd = 2.7v to 3.6v) note: t a = 25 c. parameter test conditions M28W160 unit min typ (1) max word program v pp = 12v 5% 10 s v pp = v dd 20 s main block program v pp = 12v 5% 0.24 1 sec v pp = v dd 0.8 2.4 sec parameter block program v pp = 12v 5% 0.03 0.12 sec v pp = v dd 0.1 0.3 sec main block erase v pp = 12v 5% 0.6 5 sec v pp = v dd 15 sec parameter block erase v pp = 12v 5% 0.4 4 sec v pp = v dd 0.5 4 sec program/erase cycles (per block) 100,000 cycles
M28W160t, M28W160b 12/40 block protection two parameter blocks can be protected against program or erase to ensure extra data security. for M28W160t, the blocks from address fe000h to fffffh can be protected. for M28W160b, the blocks from address 00000h to 01fffh can be protected. unprotected blocks can be pro- grammed or erased. wp tied to v il protects the two lockable blocks. any program or erase operation on protected blocks is aborted. the status register tracks when the event occurs. wp tied to v ih unprotects all the blocks that can be protect. table 9 defines the protection methods. rp tied to v il protects all blocks. power consumption the M28W160 place itself in one of four different modes depending on the status of the control sig- nals: active power, automatic power savings, standby and power down define decreasing lev- els of current consumption. these allow the mem- ory power to be minimised, in turn decreasing the overall system power consumption. as different recovery time are linked to the differ- ent modes, please refer to the ac timing table to design your system. active power when e is at v il and rp is at v ih , the device is in active mode. refer to dc characteristics to get the values of the current supply consumption. automatic stand-by automatic stand-by provides a low power con- sumption state during read mode. following a read operation, after a delay close to the memory access time, the device enters auto- matic stand-by: the supply current is reduced to i cc1 values. the device keeps the last output data stable, till a new location is accessed. stand-by refer to the device operations section. power down refer to the device operations section. power up the supply voltage v dd and the program supply voltage v pp can be applied in any order. the figure 3. otp memory area address table ai02545 00000h otp word # 0 otp word # 255 000ffh memory command interface is reset on power up to read memory array, but a negative transition of chip enable e or a change of the addresses is re- quired to ensure valid data outputs. care must be taken to avoid writes to the memory when v dd is above v lko and v pp powers up first. writes can be inhibited by driving either e or w to v ih . the memory is disabled until rp is up to v ih . supply rails normal precautions must be taken for supply volt- age decoupling, each device in a system should have the v dd and v pp rails decoupled with a 0.1f capacitor close to the v dd and v pp pins. the pcb trace widths should be sufficient to carry the re- quired v pp program and erase currents. otp memory area M28W160 features an additional "one time pro- grammable" memory area. this feature is ob- tained by means of an otp block of 256 word, which can be programmed once and cannot be erased, thus useful to store permanent data. this otp memory area can be programmed and ad- dressed in read mode by the customer through two dedicated commands. refer to the program otp area (pdo) and read otp area (rdo) in- structions to properly write and read the otp memory block. the otp memory area is organized as 256 x 16 bits as shown in the otp address table, figure 3.
13/40 M28W160t, M28W160b common flash interface (cfi) the common flash interface (cfi) specification is a jedec approved, standardised data structure that can be read from the flash memory device. cfi allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. cfi allows the system to easily interface to the flash memory, to learn about its features and pa- rameters, enabling the software to configure itself when necessary. tables 12, 13, 14, 15, 16 and 17 show the address used to retrieve each data. the cfi data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. tables 12, 13, 14 and 15 show the addresses used to retrieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique secu- rity number is written, starting at address 80h. this area can be accessed only in read mode by the fi- nal user and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode. refer to the cfi query instruction to understand how the M28W160 enters the cfi query mode. table 12. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 13, 14, 15, 16 and 17. query data are always presented on the lowest order data outputs. table 13. cfi query identification string note: query data are always presented on the lowest - order data outputs (dq7-dq0) only. dq8-dq15 are 0. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h 0091h - bottom 0090h - top device code 02h-0fh reserved reserved 10h 0051h query unique ascii string "qry" 11h 0052h query unique ascii string "qry" 12h 0059h query unique ascii string "qry" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0035h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h
M28W160t, M28W160b 14/40 table 14. cfi query system interface information offset data description 1bh 0027h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 1ch 0036h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 1dh 00b4h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv note: this value must be 0000h if no v pp pin is present 1eh 00c6h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv note: this value must be 0000h if no v pp pin is present 1fh 0005h typical timeout per single byte/word program (multi-byte program count = 1), 2 n s (if supported; 0000h = not supported) 20h 0000h typical timeout for maximum-size multi-byte program or page write, 2 n s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0007h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0000h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0003h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported)
15/40 M28W160t, M28W160b table 15. device geometry definition offset word mode data description 27h 0015h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0002h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more con- tiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is considered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are separate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. M28W160t M28W160t erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 001eh 2eh 0000h 2fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h M28W160b M28W160b 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 001eh 32h 0000h 33h 0000h 34h 0001h
M28W160t, M28W160b 16/40 table 16. primary algorithm-specific extended query table table 17. security code area offset data description (p)h = 35h 0050h primary algorithm extended query table unique ascii string pri 0052h 0049h (p+3)h = 38h 0031h major version number, ascii (p+4)h = 39h 0030h minor version number, ascii (p+5)h = 3ah 0006h extended query table contents for primary algorithm bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend (1 = yes, 0 = no) bit 3 lock/unlock supported (1 = yes, 0 = no) bit 4 quequed erase supported (1 = yes, 0 = no) bit 31 to 5 reserved; undefined bits are 0 0000h (p+7)h 0000h (p+8)h 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 (p+a)h = 3fh 0000h block lock status defines which bits in the block status register section of the query are implemented. bit 0 block lock status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 (p+b)h 0000h (p+c)h = 41h 0027h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+d)h = 42h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+e)h 0000h reserved offset data description 80h 00xx 64 pseudo random bit unique security number 81h 00xx 82h 00xx 83h 00xx 84h 00xx 85h 00xx 86h 00xx 87h 00xx
17/40 M28W160t, M28W160b table 18a. dc characteristics (t a = 0 to 70c or C40 to 85c) note: 1. current increases to i cc + i cc5 during a read operation. symbol parameter test condition v dd = 2.7v to 3.6v v ddq = 2.7v to 3.6v unit min max i li input leakage current 0v v in v dd 1 a i lo output leakage current 0v v out v dd 10 a i cc supply current (read) e = v ss , g = v ih , f = 5mhz 20 ma i cc1 supply current (standby or automatic standby) e = v dd 0.2v, rp = v dd 0.2v 10 a i cc2 supply current (power down) rp = v ss 0.2v 10 a i cc3 supply current (program) program in progress v pp = 12v 5% 20 ma program in progress v pp = v dd 20 ma i cc4 supply current (erase) erase in progress v pp = 12v 5% 20 ma erase in progress v pp = v dd 20 ma i cc5 supply current (program/erase suspend) e = v ih , erase suspended 10 a i pp program current (read or standby) v pp > v dd 200 a i pp1 program current (read or standby) v pp v dd 15 a i pp2 program current (power down) rp = v ss 0.2v 5a i pp3 program current (program) program in progress v pp = 12v 5% 15 ma program in progress v pp = v dd 20 ma i pp4 program current (erase) erase in progress v pp = 12v 5% 15 ma erase in progress v pp = v dd 20 ma i pp5 (1) program current (program/erase suspend) program/erase suspended 200 a v il input low voltage C0.4 0.4 v v ih input high voltage v ddq C0.4 v v ol output low voltage i ol = 100a, v dd = v dd min, v ddq = v ddq min 0.1 v v oh output high voltage i oh = C100a, v dd = v dd min, v ddq = v ddq min v ddq C0.1 v v pp1 program voltage (program or erase operations) 2.7 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v lko v dd supply voltage (program and erase lock-out) 2.2 v v lko2 v ddq supply voltage (program and erase lock-out) 1.5 v v pplk program voltage lock-out 1.5 v
M28W160t, M28W160b 18/40 table 18b. dc characteristics (t a = 0 to 70c or C 40 to 85c) note: 1. current increases to i cc + i cc5 during a read operation. symbol parameter test condition v dd = 2.7v to 3.3v v ddq = 1.65v min unit min max i li input leakage current 0v v in v dd 1 a i lo output leakage current 0v v out v dd 10 a i cc supply current (read) e = v ss , g = v ih , f = 5mhz 20 ma i cc1 supply current (standby or automatic standby) e = v dd 0.2v, rp = v dd 0.2v 10 a i cc2 supply current (power down) rp = v ss 0.2v 10 a i cc3 supply current (program) program in progress v pp = 12v 5% 20 ma program in progress v pp = v dd 20 ma i cc4 supply current (erase) erase in progress v pp = 12v 5% 20 ma erase in progress v pp = v dd 20 ma i cc5 supply current (program/erase suspend) e = v ih , erase suspended 10 a i pp program current (read or standby) v pp > v dd 200 a i pp1 program current (read or standby) v pp v dd 15 a i pp2 program current (power down) rp = v ss 0.2v 5a i pp3 program current (program) program in progress v pp = 12v 5% 15 ma program in progress v pp = v dd 20 ma i pp4 program current (erase) erase in progress v pp = 12v 5% 15 ma erase in progress v pp = v dd 20 ma i pp5 (1) program current (program/erase suspend) program/erase suspended 200 a v il input low voltage C0.2 0.2 v v ih input high voltage v ddq C0.2 v v ol output low voltage i ol = 100a, v dd = v dd min, v ddq = v ddq min 0.1 v v oh output high voltage i oh = C100a, v dd = v dd min, v ddq = v ddq min v ddq C0.1 v v pp1 program voltage (program or erase operations) 2.7 3.3 v v pph program voltage (program or erase operations) 11.4 12.6 v v lko v dd supply voltage (program and erase lock-out) 2.2 v v lko2 v ddq supply voltage (program and erase lock-out) 1.2 v v pplk program voltage lock-out 1.5 v
19/40 M28W160t, M28W160b figure 5. ac testing load circuit ai00609b v ddq /2 out c l = 50pf c l includes jig capacitance 3.3k w 1n914 device under test table 19. ac measurement conditions input rise and fall times 10ns input pulse voltages 0 to v ddq input and output timing ref. voltages v ddq /2 figure 4. ac testing input output waveform ai00610 v ddq 0v v ddq /2 table 20. capacitance (1) (t a = 25 c, f = 1 mhz ) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
M28W160t, M28W160b 20/40 table 21a. read ac characteristics (1) ( t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 4. the device reset is possible but not guaranteed if t plph < 100ns. symbol alt parameter M28W160 unit 100 120 v dd = 3v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.3v v ddq = 1.65v min min max min max t avav t rc address valid to next address valid 100 120 ns t av qv t acc address valid to output valid 100 120 ns t phqv t pwh power down high to output valid 200 200 ns t elqx (2) t lz chip enable low to output transition 0 0 ns t elqv (3) t ce chip enable low to output valid 100 120 ns t glqx (2) t olz output enable low to output transition 0 0 ns t glqv (3) t oe output enable low to output valid 30 35 ns t ehqx (2) t oh chip enable high to output transition 0 0 ns t ehqz (2) t hz chip enable high to output hi-z 25 30 ns t ghqx (2) t oh output enable high to output transition 0 0 ns t ghqz (2) t df output enable high to output hi-z 25 30 ns t axqx (2) t oh address transition to output transition 0 0 ns t plph (2,4) t rp rp reset pulse width 100 100 ns
21/40 M28W160t, M28W160b table 21b. read ac characteristics (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 4. the device reset is possible but not guaranteed if t plph < 100ns. symbol alt parameter M28W160 unit 150 v dd = 2.7v to 3.3v v ddq = 1.65v min min max t avav t rc address valid to next address valid 150 ns t av qv t acc address valid to output valid 150 ns t phqv t pwh power down high to output valid 200 ns t elqx (2) t lz chip enable low to output transition 0 ns t elqv (3) t ce chip enable low to output valid 150 ns t glqx (2) t olz output enable low to output transition 0 ns t glqv (3) t oe output enable low to output valid 40 ns t ehqx (2) t oh chip enable high to output transition 0 ns t ehqz (2) t hz chip enable high to output hi-z 35 ns t ghqx (2) t oh output enable high to output transition 0 ns t ghqz (2) t df output enable high to output hi-z 35 ns t axqx (2) t oh address transition to output transition 0 ns t plph (2,4) t rp rp reset pulse width 100 ns
M28W160t, M28W160b 22/40 figure 6. read ac waveforms dq0-dq15 ai00619 valid a0-a19 e rp taxqx tavav valid tavqv telqv telqx tglqv tglqx tphqv power-up and standby address valid and chip enable outputs enabled data valid standby g tghqx tghqz tehqx tehqz note: write enable (w ) = high.
23/40 M28W160t, M28W160b table 22a. write ac characteristics, write enable controlled (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the lockable blocks wp must be at v ih . 4. sampled only, not 100% tested. 5. the device reset is possible but not guaranteed if t plph < 100ns. 6. the reset will complete within 100ns if rp is asserted while not in program nor in erase m symbol alt parameter M28W160 unit 100 120 v dd = 3v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.3v v ddq = 1.65v min min max min max t avav t wc write cycle time 100 120 ns t phwl t ps power down high to write enable low 100 120 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 70 70 ns t dvwh t ds data valid to write enable high 70 70 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 30 30 ns t avwh t as address valid to write enable high 70 70 ns t wphwh write protect high to write enable high 70 70 ns t vphwh (4) t vps v pp high to write enable high 200 200 ns t whax t ah write enable high to address transition 0 0 ns t whqv1 (2, 3) write enable high to output valid 10 10 s t whqv2 (2) write enable high to output valid (parameter block erase) 4 4 sec t whqv3 (2) write enable high to output valid (main block erase) 5 5 sec t qvvpl (4) output valid to v pp not v dd nor v pph 00ns t plph (4,5) t rp rp reset pulse width 100 100 ns t plrh (4,6) rp low to program/erase abort 22 22 s
M28W160t, M28W160b 24/40 table 22b. write ac characteristics, write enable controlled (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the lockable blocks wp must be at v ih . 4. sampled only, not 100% tested. 5. the device reset is possible but not guaranteed if t plph < 100ns. 6. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. symbol alt parameter M28W160 unit 150 v dd = 2.7v to 3.3v v ddq = 1.65v min min max t avav t wc write cycle time 150 ns t phwl t ps power down high to write enable low 150 ns t elwl t cs chip enable low to write enable low 0 ns t wlwh t wp write enable low to write enable high 100 ns t dvwh t ds data valid to write enable high 100 ns t whdx t dh write enable high to data transition 0 ns t wheh t ch write enable high to chip enable high 0 ns t whwl t wph write enable high to write enable low 50 ns t avw h t as address valid to write enable high 100 ns t wphwh write protect high to write enable high 100 ns t vphwh (4) t vps v pp high to write enable high 200 ns t whax t ah write enable high to address transition 0 ns t whqv1 (2, 3) write enable high to output valid 10 s t whqv2 (2) write enable high to output valid (parameter block erase) 4 sec t whqv3 (2) write enable high to output valid (main block erase) 5 sec t qvvpl (4) output valid to v pp not v dd nor v pph 0ns t plph (4,5) t rp rp reset pulse width 100 ns t plrh (4,6) rp low to program/erase abort 22 s
25/40 M28W160t, M28W160b figure 7. write ac waveforms, w controlled e g w dq0-dq15 command cmd or data status register rp v pp valid a0-a19 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh tphwl twhwl tvphwh power-up and set-up command confirm command or data input status register read twhqv1,2,3 ai00620 twphwh wp note: command input and status register read output is on dqo-dq7 only.
M28W160t, M28W160b 26/40 table 23a. write ac characteristics, chip enable controlled (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. for program or erase of the lockable blocks wp must be at v ih . 4. sampled only, not 100% tested. 5. the device reset is possible but not guaranteed if t plph < 100ns. 6. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. symbol alt parameter M28W160 unit 100 120 v dd = 3v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.3v vddq = 1.65v min min max min max t avav t wc write cycle time 100 120 ns t phel t ps power down high to chip enable low 100 120 ns t wlel t cs write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 70 70 ns t dveh t ds data valid to chip enable high 70 70 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 10 ns t ehel t cph chip enable high to chip enable low 30 30 ns t av eh t as address valid to chip enable high 70 70 ns t wpheh write protect high to chip enable high 70 70 ns t vpheh (4) t vps v pp high to chip enable high 200 200 ns t ehax t ah chip enable high to address transition 0 0 ns t ehqv1 (2, 3) chip enable high to output valid 10 10 s t ehqv2 (2) chip enable high to output valid (parameter block erase) 4 4 sec t ehqv3 (2) chip enable high to output valid (main block erase) 5 5 sec t qvvpl (4) output valid to v pp not v dd nor v pph 00ns t plph (4,5) t rp rp reset pulse width 100 100 ns t plrh (4,6) rp low to program/erase abort 22 22 s
27/40 M28W160t, M28W160b table 23b. write ac characteristics, chip enable controlled (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. time is measured to status register read giving bit b7 = '1'. 3. .for program or erase of the lockable blocks wp must be at v ih . 4. sampled only, not 100% tested. 5. the device reset is possible but not guaranteed if t plph < 100ns. 6. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. symbol alt parameter M28W160 unit 150 v dd = 2.7v to 3.3v v ddq = 1.65v min min max t avav t wc write cycle time 150 ns t phel t ps power down high to chip enable low 150 ns t wlel t cs write enable low to chip enable low 0 ns t eleh t cp chip enable low to chip enable high 100 ns t dveh t ds data valid to chip enable high 100 ns t ehdx t dh chip enable high to data transition 0 ns t ehwh t wh chip enable high to write enable high 0 ns t ehel t cph chip enable high to chip enable low 50 ns t av eh t as address valid to chip enable high 100 ns t wpheh write protect high to chip enable high 100 ns t vpheh (4) t vps v pp high to chip enable high 200 ns t ehax t ah chip enable high to address transition 0 ns t ehqv1 (2, 3) chip enable high to output valid 10 s t ehqv3 (2) chip enable high to output valid (parameter block erase) 4 sec t ehqv4 (2) chip enable high to output valid (main block erase) 5 sec t qvvpl (4) output valid to v pp not v dd nor v pph 0ns t plph (4,5) t rp rp reset pulse width 100 ns t plrh (4,6) rp low to programerase abort 22 s
M28W160t, M28W160b 28/40 figure 8. write ac waveforms, e controlled e g dq0-dq15 command cmd or data status register rp v pp valid a0-a19 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tphel tehel tvpheh power-up and set-up command confirm command or data input status register read tehqv1,2,3 ai00621 w twpheh wp
29/40 M28W160t, M28W160b figure 9. reset/power down ac waveform ai00624 tphqv rp tplph rp tplph reset during read mode reset during program with t plph t plrh tplrh tphwl tphel abort complete rp tplph reset during program/erase with t plph > t plrh tplrh tphwl tphel abort complete power down
M28W160t, M28W160b 30/40 figure 10. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each word programming or after a sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 40h command ai00611b start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) pg instruction: C write 40h command C write address & data (memory enters read status state after the pg instruction) do: C read status register (e or g must be toggled) while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end yes no b1 = 0 program to protected block error if b1 = 1, program to protected block error: C error handler
31/40 M28W160t, M28W160b figure 11. program suspend & resume flowchart and pseudo code write 70h command ai00612 read status register yes no b7 = 1 yes no b4 = 1 program continues write ffh command pes instruction: C write b0h command (memory enters read register state after the pes instruction) do: C read status register (e or g must be toggled) while b7 = 1 if b4 = 0, program completed (at this point the memory will accept only the rd or per instruction) rd instruction: C write ffh command C one or more data reads from another block write d0h command per instruction: C write d0h command to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued). read data from another block start write b0h command program complete write ffh command read data
M28W160t, M28W160b 32/40 figure 12. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 20h command ai00613b start write block address & d0h command read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error ee instruction: C write 20h command C write block address (a12-a17) & command d0h (memory enters read status state after the ee instruction) do: C read status register (e or g must be toggled) if ee instruction given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: C error handler
33/40 M28W160t, M28W160b figure 13. erase suspend & resume flowchart and pseudo code write 70h command ai00615 read status register yes no b7 = 1 yes no b6 = 1 program continues write ffh command pes instruction: C write b0h command (memory enters read register state after the pes instruction) do: C read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed (at this point the memory wich accept only the rd or per instruction) rd instruction: C write ffh command C one o more data reads from another block write d0h command read data from another block or program start write b0h command erase complete write ffh command read data pg instruction: C write 40h command C write address & data per instruction: C write d0h command to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued).
M28W160t, M28W160b 34/40 figure 14a. command interface and program erase controller flowchart (a) note: 1. if no command is written, the command interface remains in its previous valid state. upon power-up, on exit from power-d own or if v dd falls below v lko , the command interface defaults to read array mode. 2. p/e.c. status (ready or busy) is read on status register bit 7. ai00616 read signature yes no 90h read status yes 70h no clear status yes 50h no program set-up yes 40h or 10h no erase set-up yes 20h no erase command error yes ffh wait for command write (1) read status read array yes d0h no a b no c cfi query yes 98h no
35/40 M28W160t, M28W160b figure 14b. command interface and prgogram erase controller flowchart (b) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. read status yes no 70h b erase yes ready (2) no a b0h no read status yes ready (2) no erase suspend yes d0h read array yes erase suspended read status (read status) yes no (erase resume) no read status 90h no read signature yes 98h no cfi query yes 40h or 10h no program set-up yes c ai00617
M28W160t, M28W160b 36/40 figure 14c. command interface and program erase controller flowchart (c) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. read status yes no 70h b program yes ready (2) no c b0h no read status yes ready (2) no program suspend yes d0h read array yes program suspended read status (read status) yes no (program resume) no read status 90h no read signature yes 98h no cfi query yes ai00618
37/40 M28W160t, M28W160b table 24. ordering information scheme devices are shipped from the factory with the memory content erased (to ffffh). for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: M28W160t 100 n 6 t device type m28 operating voltage w = v dd = 2.7v to 3.6v; v ddq = 1.65v or 2.7v device function 160 = 16 mbit (1mb x16), boot block array matrix t = top boot b = bottom boot random speed 100 = 100 ns 120 = 120 ns 150 = 150 ns package n = tsop48: 12 x 20 mm gj = bga48: 0.75 mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option t = tape & reel packing
M28W160t, M28W160b 38/40 table 25. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 11.90 12.10 0.469 0.476 e 0.50 C C 0.020 C C l 0.50 0.70 0.020 0.028 a 0 5 0 5 n48 48 cp 0.10 0.004 figure 15. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
39/40 M28W160t, M28W160b table 26. bga48 - 8 x 6 balls, 0.75 mm pitch, package mechanical data symb mm inches typ min max typ min max a 0.865 0.034 a1 0.200 0.150 0.250 0.008 0.006 0.010 a2 0.494 0.444 0.544 0.019 0.017 0.021 b 0.300 0.250 0.350 0.012 0.010 0.014 ddd 0.150 0.100 0.200 0.006 0.004 0.008 d 9.616 9.516 9.716 0.379 0.375 0.383 d1 3.750 C C 0.148 C C e 0.750 C C 0.030 C C e 6.850 6.750 6.950 0.270 0.266 0.274 e1 5.250 C C 0.207 C C sd 0.375 C C 0.015 C C se 0.375 C C 0.015 C C figure 16. bga48 - 8 x 6 balls, 0.75 mm pitch, package outline drawing is not to scale. d1 d e1 e eb se sd a2 a1 a bga-g01 ddd ball "a1"
M28W160t, M28W160b 40/40 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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